Samsung researchers have published a detailed account of an experimental NAND architecture that aims to cut one of the technology’s largest power drains by as much as 96%.
The work — data-analytics-id=”inline-link” href=”https://go.redirectingat.com?id=92X1584492&xcust=tomshardware_us_1161340090719704646&xs=1&url=https%3A%2F%2Fwww.nature.com%2Farticles%2Fs41586-025-09793-3&sref=https%3A%2F%2Fwww.tomshardware.com%2Ftech-industry%2Fsemiconductors%2Fsamsung-researchers-publish-96percent-lower-power-nand-design-based-on-ferroelectric-transistors” target=”_blank” data-url=”https://www.nature.com/articles/s41586-025-09793-3″ referrerpolicy=”no-referrer-when-downgrade” rel=”sponsored noopener” data-hl-processed=”skimlinks” data-google-interstitial=”false” data-placeholder-url=”https://go.redirectingat.com?id=92X1584492&xcust=hawk-custom-tracking&xs=1&url=https%3A%2F%2Fwww.nature.com%2Farticles%2Fs41586-025-09793-3&sref=https%3A%2F%2Fwww.tomshardware.com%2Ftech-industry%2Fsemiconductors%2Fsamsung-researchers-publish-96percent-lower-power-nand-design-based-on-ferroelectric-transistors” data-mrf-recirculation=”inline-link”>Ferroelectric transistor for low-power NAND flash memory —was carried out by researchers at the Samsung Advanced Institute of Technology and appears in the journal Nature. It describes a ferroelectric field-effect transistor (FeFET) design intended for future 3D NAND, combining a hafnia-based ferroelectric with an…
